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    • Story Points:
      8
    • Sprint:
      2019 B, 2019 C, SM1-2019 E, SM1-2019 F, SM1-2019 G

      Description

      The new ADC cards appear mostly identical to the old ones. There are a couple of exceptions which we need to track. I am hoping to use the serial numbers to automatically switch between types.

      • IR has opposite polarity. This will remove the need for the changes in INSTRM-486, but will require different a different clocking routine.
      • the bias setting circuitry is different, and presumably simpler.
      • we keep and use the sign bit from the 18-bit ADCs, so the FPGAs needs to drop the bottom two bits instead of the sign bit and the lowest bit. [ Sadly the ADCs are crappy enough that there is no gain to be had from keeping more than 16 bits. ] The FPGA already supports this, but that code may never have been tested. If we need a new FPGA image I'll make a separate ticket.

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          hassan hassan added a comment -

          Remains open while the design is still open. May be broken into smaller tickets.

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          hassan hassan added a comment - Remains open while the design is still open. May be broken into smaller tickets.
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          cloomis cloomis added a comment -

          ics_ccdActor: merged at 065e5f2, tagged 1.3.12
          ics_xcu_fpga: merged at c4edc7c, tagged 82.0.0

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          cloomis cloomis added a comment - ics_ccdActor: merged at 065e5f2, tagged 1.3.12 ics_xcu_fpga: merged at c4edc7c, tagged 82.0.0

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            • Assignee:
              cloomis cloomis
              Reporter:
              cloomis cloomis
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