[INSTRM-117] Clock serials during parallel shifts Created: 27/May/17 Updated: 30/May/18 Resolved: 30/May/18 |
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| Status: | Done |
| Project: | Instrument control development |
| Component/s: | ics_xcu_fpga |
| Affects Version/s: | None |
| Fix Version/s: | None |
| Type: | Task | Priority: | Major |
| Reporter: | cloomis | Assignee: | cloomis |
| Resolution: | Done | Votes: | 0 |
| Labels: | None | ||
| Remaining Estimate: | Not Specified | ||
| Time Spent: | Not Specified | ||
| Original Estimate: | Not Specified | ||
| Description |
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There is a substantial amount of signal at the start of each row, which decays over 30 pixels or so. This is likely because the serial clocks are idle during the parallel shifts. Make the individual parallel phases an integral factor (3) of the pixel clocking, and incorporate the non-shifting/converting pixel clocks. |
| Comments |
| Comment by cloomis [ 01/Jun/17 ] |
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We changed each ~40us parallel phase to include three 13.940us pixel clockings, and the signal is very nearly gone at 8 pixels in, which is the number if unused leadin pixels. I'll try a couple more things to see if I can get it all the way down, but it probably does not matter. |
| Comment by hassan [ 30/May/18 ] |
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Issue fixed. |