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Type: Task
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Status: Done (View Workflow)
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Priority: Major
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Resolution: Done
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Component/s: ics_xcu_fpga
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Labels:None
There is a substantial amount of signal at the start of each row, which decays over 30 pixels or so. This is likely because the serial clocks are idle during the parallel shifts.
Make the individual parallel phases an integral factor (3) of the pixel clocking, and incorporate the non-shifting/converting pixel clocks.