Some BEEs have slow readout.

On some BEEs, CCD readout is unexpectedly slow: ~90s vs. ~34s. The problem is between the BEE and the FPGA: the readouts and DAQ are fine.

The r1 system at LAM is known to be slow, as is/was one of the optics lab systems. All the new systems I have tried appear to be OK.

Main suspects are the PCI bus configuration/operation and FPGA clock domains.

This ticket is mostly a place me to gather notes.