https://pfspipe.ipmu.jp/jira This file is an XML representation of an issue en-us 8.3.4 803005 13-09-2019 https://pfspipe.ipmu.jp/jira/browse/INSTRM-832 Instrument control development <p>The FPGA clock description does not separate logical from electronic polarity. "turn IR on" always drives the signal high, instead of always closing the switch. This has occasionally been confusing, but the requirement to support two versions of the ADC board, one with normally-open switches and one with normally-closed switches makes it nutty.</p> <p>Add a polarity flag to the low-level clock class, and allow overriding for the old ADCs.</p> <p>I fixed <a href="https://pfspipe.ipmu.jp/jira/browse/INSTRM-709" title="Allow new ics_xcu_fpga code to run with old ADC boards." class="issue-link" data-issue-key="INSTRM-709"><del>INSTRM-709</del></a> without this, using a simpler mechanism. Would still be worth doing, but is no longer a blocker.</p> INSTRM-832

Add polarity to FPGA clock description

Task Minor Open Unresolved cloomis cloomis SPS Tue, 3 Dec 2019 21:17:37 +0000 Wed, 3 Jun 2020 15:46:19 +0000 ics_xcu_fpga 0 1 Development Rank 0|02qpuc:i6001gr068fhw9qr Sprint SM1PD-2020 A Story Points 1.0