[INSTRM-642] Adapt to new gatevalve interlock hardware and logic

Wed, 5 Jun 2019 13:38:39 +0000

The new gatevalve controller logic follows, per email. As far as safety goes, this takes over nearly all of the existing logic in the software. We still need to run (but modify) most of the gatevalve open code, since that is what tells humans understandable diagnostics.

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The new board has logic and a PIC… The logic for allowing the gate valve to open is as follows:

GATE VALVE SOLENOID = OPEN & (TURBO_UPTO_SPEED | TURBO_OVERRIDE) & !TURBO_LOCKOUT & (PRESSURE_EQUAL | GATE_VALVE_OPEN) & PCM_24V

TURBO_OVERRIDE is a latch, and is set when OPEN low, and cleared when turbo is up to speed.
TURBO_ LOCKOUT is a latch, and is cleared when open is low, disabled when TURBO_OVERRIDE is high, and set when TURBO_UPTO_SPEED drops out.

All of the above is determined by logic gates, with the exception of the PRESSURE_EQUAL input, which is controlled by the PIC. The PIC will read 2 pressure sensors either side of the gate valve to make this determination. The logic overrides this signal once the gate valve is open.

The PIC will also monitor the logic. The signals it will monitor are:

OPEN
GATE_VALVE_OPEN
GATE_VALVE_CLOSED
TURBO_UPTO_SPEED
DEWAR_PRESSURE
ROUGHING_PRESSURE
GATE_VALVE_SOLENOID

You will have a similar interface to before… You will control the OPEN signal, and monitor the GATE_VALVE_SOLENOID signal. You will no longer get GVO or GVC. Instead you will get access to all signals via an RS232 port.

You will still need to assert the port on the PCM to allow the gate valve to be energized. This will be your secondary means of locking the gate valve.

PFS-JIRA

[INSTRM-642] Adapt to new gatevalve interlock hardware and logic