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        <build-number>803005</build-number>
        <build-date>13-09-2019</build-date>
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<item>
            <title>[INSTRM-616] Adapt to new ADC cards</title>
                <link>https://pfspipe.ipmu.jp/jira/browse/INSTRM-616</link>
                <project id="10300" key="INSTRM">Instrument control development</project>
                    <description>&lt;p&gt;The new ADC cards appear &lt;em&gt;mostly&lt;/em&gt; identical to the old ones. There are a couple of exceptions which we need to track. I am hoping to use the serial numbers to automatically switch between types.&lt;/p&gt;

&lt;ul class=&quot;alternate&quot; type=&quot;square&quot;&gt;
	&lt;li&gt;IR has opposite polarity. This will remove the need for the changes in &lt;a href=&quot;https://pfspipe.ipmu.jp/jira/browse/INSTRM-486&quot; title=&quot;Ensure that the ADC switches are configured when LVDS is enabled&quot; class=&quot;issue-link&quot; data-issue-key=&quot;INSTRM-486&quot;&gt;&lt;del&gt;INSTRM-486&lt;/del&gt;&lt;/a&gt;, but will require different a different clocking routine.&lt;/li&gt;
	&lt;li&gt;the bias setting circuitry is different, and presumably simpler.&lt;/li&gt;
	&lt;li&gt;we keep and use the sign bit from the 18-bit ADCs, so the FPGAs needs to drop the bottom two bits instead of the sign bit and the lowest bit.  [ Sadly the ADCs are crappy enough that there is no gain to be had from keeping more than 16 bits. ] The FPGA already supports this, but that code may never have been tested. If we need a new FPGA image I&apos;ll make a separate ticket.&lt;/li&gt;
&lt;/ul&gt;
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                <environment></environment>
        <key id="13375">INSTRM-616</key>
            <summary>Adapt to new ADC cards</summary>
                <type id="3" iconUrl="https://pfspipe.ipmu.jp/jira/secure/viewavatar?size=xsmall&amp;avatarId=10518&amp;avatarType=issuetype">Task</type>
                                            <priority id="10000" iconUrl="https://pfspipe.ipmu.jp/jira/images/icons/priorities/medium.svg">Normal</priority>
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                                    <resolution id="10000">Done</resolution>
                                        <assignee username="cloomis">cloomis</assignee>
                                    <reporter username="cloomis">cloomis</reporter>
                        <labels>
                            <label>SM1</label>
                    </labels>
                <created>Mon, 25 Feb 2019 12:22:23 +0000</created>
                <updated>Wed, 15 May 2019 12:46:27 +0000</updated>
                            <resolved>Mon, 13 May 2019 23:24:18 +0000</resolved>
                                                                    <component>ics_ccdActor</component>
                    <component>ics_xcu_fpga</component>
                        <due></due>
                            <votes>0</votes>
                                    <watches>2</watches>
                                                                <comments>
                            <comment id="15351" author="hassan" created="Wed, 24 Apr 2019 15:22:44 +0000"  >&lt;p&gt;Remains open while the design is still open. May be broken into smaller tickets.&lt;/p&gt;</comment>
                            <comment id="15445" author="cloomis" created="Mon, 13 May 2019 23:24:19 +0000"  >&lt;p&gt;ics_ccdActor: merged at 065e5f2, tagged 1.3.12&lt;br/&gt;
ics_xcu_fpga: merged at c4edc7c, tagged 82.0.0&lt;/p&gt;</comment>
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