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        <build-date>13-09-2019</build-date>
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<item>
            <title>[INSTRM-5] CCD amp columns</title>
                <link>https://pfspipe.ipmu.jp/jira/browse/INSTRM-5</link>
                <project id="10300" key="INSTRM">Instrument control development</project>
                    <description>&lt;p&gt;The amp geometry in the current readouts is slightly wrong.&lt;/p&gt;

&lt;p&gt;The physical geometry, as detailed in the Hamamatsu  docs, is:&lt;/p&gt;

&lt;p&gt;. 8 leadin pixels&lt;br/&gt;
. 512 image pixels&lt;/p&gt;

&lt;p&gt;We currently request 32 pixels of overscan. For all amps, the images show:&lt;/p&gt;

&lt;p&gt;. 9 leadin pixels&lt;br/&gt;
. 512 image pixels&lt;br/&gt;
. 31 overscan pixels&lt;/p&gt;

&lt;p&gt;From the pixels levels, which vary slightly between amps, it appears that the 0th leadin pixel in the amp image is actually an overscan pixel, presumably the last one.&lt;/p&gt;

&lt;p&gt;The current image headers do not have a geometry version number. I suggest that we adjust the stack ISR routines to drop 9 pixels and use 31 pixels of overscan for such files (geometry version 0, call them). Subsequent images from the acquisition software should correct this problem and set the version number to &amp;gt;= 1. When the ISR sees that, it should &lt;em&gt;not&lt;/em&gt; correct.&lt;/p&gt;

&lt;p&gt;If such a procedure would be too difficult, we can rewrite existing data: none of it has been created outside a lab, and there are only a few hundred real images.&lt;/p&gt;

&lt;p&gt;If you want to confirm this, i&apos;ll suggest one of the lab flats, say 2015-12-22/PFSA00722192.fits. Yes I know that should be PFLA.&lt;/p&gt;</description>
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        <key id="11154">INSTRM-5</key>
            <summary>CCD amp columns</summary>
                <type id="1" iconUrl="https://pfspipe.ipmu.jp/jira/secure/viewavatar?size=xsmall&amp;avatarId=10503&amp;avatarType=issuetype">Bug</type>
                                            <priority id="3" iconUrl="https://pfspipe.ipmu.jp/jira/images/icons/priorities/major.svg">Major</priority>
                        <status id="10002" iconUrl="https://pfspipe.ipmu.jp/jira/images/icons/statuses/generic.png" description="The issue is resolved, reviewed, and merged">Done</status>
                    <statusCategory id="3" key="done" colorName="green"/>
                                    <resolution id="10000">Done</resolution>
                                        <assignee username="cloomis">cloomis</assignee>
                                    <reporter username="cloomis">cloomis</reporter>
                        <labels>
                    </labels>
                <created>Wed, 21 Sep 2016 18:21:46 +0000</created>
                <updated>Mon, 11 Jun 2018 18:35:45 +0000</updated>
                            <resolved>Fri, 13 Oct 2017 08:12:51 +0000</resolved>
                                                                        <due></due>
                            <votes>0</votes>
                                    <watches>1</watches>
                                                                <comments>
                            <comment id="11320" author="cloomis" created="Wed, 21 Sep 2016 19:41:14 +0000"  >&lt;p&gt;Jim reminded me that a single inserted pixel would do this. If so I think the problem is in the FPGA since that is where the complete rows are constructed, including a row CRC and a &quot;row sync&quot; word. I don&apos;t see any way for the host software to treat the 0th row differently from others.&lt;/p&gt;
</comment>
                            <comment id="12662" author="cloomis" created="Fri, 13 Oct 2017 08:12:51 +0000"  >&lt;p&gt;This is fixed up in ics_xcu_fpga. Tagged 70.3.0&lt;/p&gt;</comment>
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