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    <title>PFS-JIRA</title>
    <link>https://pfspipe.ipmu.jp/jira</link>
    <description>This file is an XML representation of an issue</description>
    <language>en-us</language>    <build-info>
        <version>8.3.4</version>
        <build-number>803005</build-number>
        <build-date>13-09-2019</build-date>
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<item>
            <title>[INSTRM-1526] Implement internal FEE routine for LBNL wipe</title>
                <link>https://pfspipe.ipmu.jp/jira/browse/INSTRM-1526</link>
                <project id="10300" key="INSTRM">Instrument control development</project>
                    <description>&lt;p&gt;[ I thought I had filed this earlier but apparently not. ]&lt;/p&gt;

&lt;p&gt;The LBNL wipe routine is believed to ameliorate the tearing seen in &lt;a href=&quot;https://pfspipe.ipmu.jp/jira/browse/INSTRM-7&quot; title=&quot;CCD flats show regions of vertical structure from top of detector&quot; class=&quot;issue-link&quot; data-issue-key=&quot;INSTRM-7&quot;&gt;&lt;del&gt;INSTRM-7&lt;/del&gt;&lt;/a&gt;. We have a been using an external loop which is slow. Implement an internal routine instead. Specifically:&lt;/p&gt;

&lt;ul class=&quot;alternate&quot; type=&quot;square&quot;&gt;
	&lt;li&gt;Push parallels up to some newly specified voltage&lt;/li&gt;
	&lt;li&gt;Ramp Vbb down to zero volts at a specified rate&lt;/li&gt;
	&lt;li&gt;Dwell for 0.5 seconds&lt;/li&gt;
	&lt;li&gt;Ramp Vbb back up to its original voltage at the same rate&lt;/li&gt;
	&lt;li&gt;When Vbb reaches  a defined  threshold, drop the parallels to their original value&lt;/li&gt;
	&lt;li&gt;Continue ramping Vbb&lt;/li&gt;
&lt;/ul&gt;


&lt;p&gt;So command like:&lt;/p&gt;

&lt;p&gt;&lt;tt&gt;~SEQ,&lt;span class=&quot;error&quot;&gt;&amp;#91;ramp_time_ms&amp;#93;&lt;/span&gt;,&lt;span class=&quot;error&quot;&gt;&amp;#91;threshold&amp;#93;&lt;/span&gt;,&lt;span class=&quot;error&quot;&gt;&amp;#91;parallel voltage&amp;#93;&lt;/span&gt;&lt;/tt&gt;&lt;/p&gt;</description>
                <environment></environment>
        <key id="22637">INSTRM-1526</key>
            <summary>Implement internal FEE routine for LBNL wipe</summary>
                <type id="3" iconUrl="https://pfspipe.ipmu.jp/jira/secure/viewavatar?size=xsmall&amp;avatarId=10518&amp;avatarType=issuetype">Task</type>
                                            <priority id="10000" iconUrl="https://pfspipe.ipmu.jp/jira/images/icons/priorities/medium.svg">Normal</priority>
                        <status id="10002" iconUrl="https://pfspipe.ipmu.jp/jira/images/icons/statuses/generic.png" description="The issue is resolved, reviewed, and merged">Done</status>
                    <statusCategory id="3" key="done" colorName="green"/>
                                    <resolution id="10000">Done</resolution>
                                        <assignee username="shope">shope</assignee>
                                    <reporter username="cloomis">cloomis</reporter>
                        <labels>
                            <label>SPS</label>
                    </labels>
                <created>Wed, 23 Feb 2022 14:20:29 +0000</created>
                <updated>Wed, 27 Apr 2022 15:49:52 +0000</updated>
                            <resolved>Wed, 27 Apr 2022 15:49:52 +0000</resolved>
                                                                    <component>ics_xcu_fee</component>
                        <due></due>
                            <votes>0</votes>
                                    <watches>1</watches>
                                                                <comments>
                            <comment id="30498" author="cloomis" created="Wed, 23 Feb 2022 14:21:13 +0000"  >&lt;p&gt;Implemented in Firmware Rev: 220211-01&lt;/p&gt;

&lt;p&gt;Adds the following command:&lt;/p&gt;

&lt;p&gt;rSeq,&lt;span class=&quot;error&quot;&gt;&amp;#91;new parallel voltage&amp;#93;&lt;/span&gt;,&lt;span class=&quot;error&quot;&gt;&amp;#91;Vthreshold to revert Parallels&amp;#93;&lt;/span&gt;,&lt;span class=&quot;error&quot;&gt;&amp;#91;number of ~5ms steps to ramp Vbb&amp;#93;&lt;/span&gt;,&lt;span class=&quot;error&quot;&gt;&amp;#91;Vbb dwell time in ms at 0V&amp;#93;&lt;/span&gt;\n&lt;/p&gt;

&lt;p&gt;Example:&lt;/p&gt;

&lt;p&gt;rSeq,8,8,100,1000\n&lt;br/&gt;
rSeq: Run Sequence&lt;br/&gt;
8: Set Parallels to 8V (this is an ascii float value)&lt;br/&gt;
8: Set the Vbb positive Ramp threshold for reverting parallels to 8V (this is an ascii float)&lt;br/&gt;
100: Set the number of ramp steps to 100, which approximates to 500ms (this is an ascii int)&lt;br/&gt;
1000: Set the Dwell time to 1000, which approximates to 1000ms (this is an ascii int)&lt;br/&gt;
\n: Execute the command.&lt;/p&gt;</comment>
                            <comment id="30499" author="cloomis" created="Wed, 23 Feb 2022 14:25:58 +0000"  >&lt;p&gt;And it turns out that &lt;b&gt;all&lt;/b&gt; of this might have been unnecessary. The VBB circuit had a diode which was blocking some part of the charging, and so VBB was taking a very long time to drop to 0V. So it may well be that the only thing I was doing was inserting a very long time while VBB was going from 30V to 0V. In any case we have a new knob.&lt;/p&gt;</comment>
                            <comment id="30500" author="cloomis" created="Wed, 23 Feb 2022 14:27:33 +0000"  >&lt;p&gt;Needs burning and testing.&lt;/p&gt;</comment>
                            <comment id="30778" author="cloomis" created="Wed, 27 Apr 2022 15:49:52 +0000"  >&lt;p&gt;We are calling this and it evidently works.&lt;/p&gt;</comment>
                    </comments>
                <issuelinks>
                            <issuelinktype id="10003">
                    <name>Relates</name>
                                            <outwardlinks description="relates to">
                                        <issuelink>
            <issuekey id="22690">INSTRM-1556</issuekey>
        </issuelink>
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            <issuekey id="11157">INSTRM-7</issuekey>
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