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        <build-number>803005</build-number>
        <build-date>13-09-2019</build-date>
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<item>
            <title>[INSTRM-1264] FPGA time-out during cobra operation</title>
                <link>https://pfspipe.ipmu.jp/jira/browse/INSTRM-1264</link>
                <project id="10300" key="INSTRM">Instrument control development</project>
                    <description>&lt;p&gt;FPGA time-out is encountered during the cobra operation.  It says it exceed 30.03 second timing.  When this time out happened.   The convergence test becomes very slow.&lt;/p&gt;</description>
                <environment></environment>
        <key id="15583">INSTRM-1264</key>
            <summary>FPGA time-out during cobra operation</summary>
                <type id="3" iconUrl="https://pfspipe.ipmu.jp/jira/secure/viewavatar?size=xsmall&amp;avatarId=10518&amp;avatarType=issuetype">Task</type>
                                            <priority id="10000" iconUrl="https://pfspipe.ipmu.jp/jira/images/icons/priorities/medium.svg">Normal</priority>
                        <status id="10100" iconUrl="https://pfspipe.ipmu.jp/jira/images/icons/statuses/generic.png" description="No further work should be done on this.">Won&apos;t Fix</status>
                    <statusCategory id="3" key="done" colorName="green"/>
                                    <resolution id="2">Won&apos;t Fix</resolution>
                                        <assignee username="-1">Unassigned</assignee>
                                    <reporter username="chyan">chyan</reporter>
                        <labels>
                            <label>PFI</label>
                    </labels>
                <created>Tue, 4 May 2021 08:14:00 +0000</created>
                <updated>Thu, 23 Feb 2023 09:13:57 +0000</updated>
                            <resolved>Thu, 23 Feb 2023 09:13:57 +0000</resolved>
                                                                        <due></due>
                            <votes>0</votes>
                                    <watches>2</watches>
                                                                <comments>
                            <comment id="19254" author="chyan" created="Tue, 4 May 2021 08:18:35 +0000"  >&lt;p&gt;@hassan, I think I put this ticket in wrong project.  Would you please put this ticket under ICS?&lt;/p&gt;</comment>
                            <comment id="19255" author="cloomis" created="Tue, 4 May 2021 08:18:48 +0000"  >&lt;p&gt;Please check the fpgaProtocol.log and look for any extreme requests (large number of steps, etc).&lt;/p&gt;</comment>
                            <comment id="19266" author="chyan" created="Wed, 5 May 2021 02:45:32 +0000"  >&lt;p&gt;By looking at the log on the day time-out happened.  We see many &lt;br/&gt;
&apos;TLM 1 cmdNum= 0 error= 1 0 Timeout&apos;&lt;br/&gt;
in fpgaProtocol.log.   I am guessing this may due to the wrong geometry of corba, so that software sending wrong step numbers.  I will see if this issue gone after we done the phi and theta arm calibration correctly.&lt;/p&gt;</comment>
                            <comment id="32297" author="chyan" created="Thu, 23 Feb 2023 09:13:57 +0000"  >&lt;p&gt;ticket closed since there is no way for quick and has not happen for a while&lt;/p&gt;</comment>
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