https://pfspipe.ipmu.jp/jira This file is an XML representation of an issue en-us 8.3.4 803005 13-09-2019 https://pfspipe.ipmu.jp/jira/browse/INSTRM-117 Instrument control development <p>There is a substantial amount of signal at the start of each row, which decays over 30 pixels or so. This is likely because the serial clocks are idle during the parallel shifts. </p> <p>Make the individual parallel phases an integral factor (3) of the pixel clocking, and incorporate the non-shifting/converting pixel clocks.</p> INSTRM-117

Clock serials during parallel shifts

Task Major Done Done cloomis cloomis Fri, 26 May 2017 19:53:17 +0000 Tue, 29 May 2018 21:17:35 +0000 Tue, 29 May 2018 21:17:35 +0000 ics_xcu_fpga 0 1 <p>We changed each ~40us parallel phase to include three 13.940us pixel clockings, and the signal is very nearly gone at 8 pixels in, which is the number if unused leadin pixels. I'll try a couple more things to see if I can get it all the way down, but it probably does not matter.</p> <p>Issue fixed.</p> Development Rank 0|ii023j: