https://pfspipe.ipmu.jp/jira This file is an XML representation of an issue en-us 8.3.4 803005 13-09-2019 https://pfspipe.ipmu.jp/jira/browse/INSTRM-100 Instrument control development <p>On some BEEs, CCD readout is unexpectedly slow: ~90s vs. ~34s. The problem is between the BEE and the FPGA: the readouts and DAQ are fine.</p> <p>The r1 system at LAM is known to be slow, as is/was one of the optics lab systems. All the new systems I have tried appear to be OK.</p> <p>Main suspects are the PCI bus configuration/operation and FPGA clock domains. </p> <p>This ticket is mostly a place me to gather notes.</p> INSTRM-100

Some BEEs have slow readout.

Task Major Done Done cloomis cloomis Fri, 17 Feb 2017 19:41:29 +0000 Mon, 2 Oct 2017 20:56:55 +0000 Mon, 2 Oct 2017 20:56:55 +0000 ics_xcu_fpga 0 1 <p>LAM's r1 used the original stripped-down yocto-based Debian. All new systems use a Debian 8 system with most development and system tools. The FPGA image has not been changed. The FEE image has, but it is hard to see how that would affect anything.</p> <p>Readouts using several new systems (b1, r2, the bench b9, and the r1v2 being sent to LAM) do not have the problem. Umm, from inside <tt>ics_xcu_fga</tt>:</p> <div class="preformatted panel" style="border-width: 1px;"><div class="preformattedContent panelContent"> <pre>In [1]: import clocks In [2]: pfsClocks = clocks.read.readClocks In [3]: import fpga.ccd as ccdMod In [4]: ccd = ccdMod.CCD(spectroId=9, dewarId='b', adc18bit=1) In [5]: im = ccd.readImage(clockFunc=pfsClocks) [ .... ] readTime = 34.2641; expected 34.1021 </pre> </div></div> <p>[ The 0.16s is probably due to an error waiting at the very end of the readout, and is not relevant. ]</p> <p>Found to be associated with the BEE board revision. All three older boards have been retired.</p> Development Rank 0|ii01vb: