[INSTRM-722] update DAQ test procedure for new ADC and fake CCDs Created: 01/Aug/19 Updated: 08/Oct/20 Resolved: 08/Oct/20 |
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| Status: | Won't Fix |
| Project: | Instrument control development |
| Component/s: | ics_xcu_fpga |
| Affects Version/s: | None |
| Fix Version/s: | None |
| Type: | Task | Priority: | Normal |
| Reporter: | cloomis | Assignee: | cloomis |
| Resolution: | Won't Fix | Votes: | 0 |
| Labels: | SPS | ||
| Remaining Estimate: | Not Specified | ||
| Time Spent: | Not Specified | ||
| Original Estimate: | Not Specified | ||
| Story Points: | 1 |
| Description |
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There is a set of bench tests for the CCD DAQ chains at JHU. One early test checks the behavior of the two ADC offset voltages by reading raw images with the offsets zeroed, setting the offset voltages, and confirming that the resulting bias level is as expected. With the new ADCs the scales and ranges are different. The resistors on the fake CCDs need to be modified to provide a non-0 signal level, at which point the code can be fixed. Minor change, but essential for ADC testing (note Josh Peebles), and cannot be done until the fake CCD work. |
| Comments |
| Comment by hassan [ 08/Oct/20 ] |
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Following discussions with cloomis today. |