[INSTRM-5] CCD amp columns Created: 22/Sep/16 Updated: 12/Jun/18 Resolved: 13/Oct/17 |
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| Status: | Done |
| Project: | Instrument control development |
| Component/s: | None |
| Affects Version/s: | None |
| Fix Version/s: | None |
| Type: | Bug | Priority: | Major |
| Reporter: | cloomis | Assignee: | cloomis |
| Resolution: | Done | Votes: | 0 |
| Labels: | None | ||
| Remaining Estimate: | Not Specified | ||
| Time Spent: | Not Specified | ||
| Original Estimate: | Not Specified | ||
| Sprint: | 2017-10A |
| Description |
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The amp geometry in the current readouts is slightly wrong. The physical geometry, as detailed in the Hamamatsu docs, is: . 8 leadin pixels We currently request 32 pixels of overscan. For all amps, the images show: . 9 leadin pixels From the pixels levels, which vary slightly between amps, it appears that the 0th leadin pixel in the amp image is actually an overscan pixel, presumably the last one. The current image headers do not have a geometry version number. I suggest that we adjust the stack ISR routines to drop 9 pixels and use 31 pixels of overscan for such files (geometry version 0, call them). Subsequent images from the acquisition software should correct this problem and set the version number to >= 1. When the ISR sees that, it should not correct. If such a procedure would be too difficult, we can rewrite existing data: none of it has been created outside a lab, and there are only a few hundred real images. If you want to confirm this, i'll suggest one of the lab flats, say 2015-12-22/PFSA00722192.fits. Yes I know that should be PFLA. |
| Comments |
| Comment by cloomis [ 22/Sep/16 ] |
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Jim reminded me that a single inserted pixel would do this. If so I think the problem is in the FPGA since that is where the complete rows are constructed, including a row CRC and a "row sync" word. I don't see any way for the host software to treat the 0th row differently from others. |
| Comment by cloomis [ 13/Oct/17 ] |
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This is fixed up in ics_xcu_fpga. Tagged 70.3.0 |