This issue was initially filed into JIRA by 'cloomis' at 01/Oct/15 4:09 PM as ICS-18.
This issue was assigned to 'unassigned', set as '2015-10 Detector Readout' sprint.

All the non-readout parts of the dewar control have been pulled into the "xcuActor" (turbo, coolers, temperatures, heaters, gate valve, motors and PCM power control of most of those).

FEE and FPGA control are what's left, and they need an actor.

So far I have controlled readouts using ipython notebooks in the ics_xcu_fpga product. I'm not sure how to structure the rest of the work, but the parts are:

• the FEE, which controls the voltages and wraps the CCD temperature readout. The FEE is controlled via a serial port on the BEE, and powered via a PCM port. The command structure is messy and not very synchronous, but the ics_xcu_fpga feeControl module works OK.
• the FPGA, which controls the detector clocks and provides pixel readout. This is controlled over the PCI bus with the cython FPGA module, and works OK.

The command structure is pretty obvious:

• expose @(bias|dark|science|arc|flat) etc.
• exposure @(stop|discard|recover)
• exposure @(pause|resume)
• engineering commands

Need to decide on the flushing, fast erase, windowing, binning, logic and state.

The ics_xcu_fpga modules and the ipython notebook already handle much of this, including correct filename management, so this is not Critical even for the 2015-10 detector work at LAM, but it would be very very nice to have.