By physical constraints, specifically from the CCD cables which were not unplugged. The serial stream of pixels is defined by the hardware chaining of the ADCs, and I'm wondering about how that could get "out of step". Fascinating.

Setting the CDS offsets on one amp confirmed that the live pixels on the left of the image are from CCD1, not CCD0.

A few more tests established that the CCD is fine, but that the FPGA probably is not. Specifically, the FPGA accepts two LVDS ADC inputs from the FEE, one for each CCD. Both of the FEE ADC outputs showed good data when plugged into the "ADC 0" input on the FPGA (i.e. either the left or the right CCD image was saved in left side of the image file). But the "ADC 1" (right side of the image) input showed 64k regardless of the input.

The working ADC0 LVDS input pair showed ~200 ohms (LVDS standard is 100). The non-working ADC1 pair showed ~100 ohms. More confusing than not.

We tested a new BEE + FPGA pair at JHU – both actors ran, both ADC inputs were good, the gatevalve operated, and the turbo link worked. That is being shipped to LAM. Commit 47b8fa7 of ics_dnsmasq.d has the new bee-r1 address.

Please close this after testing the new hardware at LAM.

tests done at LAM with the new BEE + FPGA.
works fine
both ccds are in the correct place.

bias taken : id 3138 to 3152

ccd R1 is working fine now, problem was due to FPGA board.