A few of the H4 voltages are configured with a "single-stage" DAC, which means that they do not really get set to the values you want, and we do not even understand the values read back. The intent is somehow to lower noise, but no one believes that noise is significant.

This matters because the voltages so configured are not the same on the two ASIC images we use for development.

We have decided to use the Teledyne conventions for now, and to apply those to the IRP/PFS image.

Will start using the pfs_utils/instdata persistence.