Clocking was done pretty badly, by literally and and thoughtlessly encoding a design which made sense to EEs. And specifically by shifting rows at the end of each row and shifting pixels at the end of each read.

So we have an extra leading pixel for each amp, and an extra row at the bottom and a missing row at the top. The pixel has been dealt with, but the row still need to be corrected.

This does not require a new FPGA, just new clocking. Will need to get the book-keeping right for DRP, etc.