[INSTRM-100] Some BEEs have slow readout. Created: 18/Feb/17 Updated: 03/Oct/17 Resolved: 03/Oct/17 |
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| Status: | Done |
| Project: | Instrument control development |
| Component/s: | ics_xcu_fpga |
| Affects Version/s: | None |
| Fix Version/s: | None |
| Type: | Task | Priority: | Major |
| Reporter: | cloomis | Assignee: | cloomis |
| Resolution: | Done | Votes: | 0 |
| Labels: | None | ||
| Remaining Estimate: | Not Specified | ||
| Time Spent: | Not Specified | ||
| Original Estimate: | Not Specified | ||
| Description |
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On some BEEs, CCD readout is unexpectedly slow: ~90s vs. ~34s. The problem is between the BEE and the FPGA: the readouts and DAQ are fine. The r1 system at LAM is known to be slow, as is/was one of the optics lab systems. All the new systems I have tried appear to be OK. Main suspects are the PCI bus configuration/operation and FPGA clock domains. This ticket is mostly a place me to gather notes. |
| Comments |
| Comment by cloomis [ 18/Feb/17 ] |
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LAM's r1 used the original stripped-down yocto-based Debian. All new systems use a Debian 8 system with most development and system tools. The FPGA image has not been changed. The FEE image has, but it is hard to see how that would affect anything. Readouts using several new systems (b1, r2, the bench b9, and the r1v2 being sent to LAM) do not have the problem. Umm, from inside ics_xcu_fga: In [1]: import clocks
In [2]: pfsClocks = clocks.read.readClocks
In [3]: import fpga.ccd as ccdMod
In [4]: ccd = ccdMod.CCD(spectroId=9, dewarId='b', adc18bit=1)
In [5]: im = ccd.readImage(clockFunc=pfsClocks)
[ .... ]
readTime = 34.2641; expected 34.1021
[ The 0.16s is probably due to an error waiting at the very end of the readout, and is not relevant. ] |
| Comment by cloomis [ 03/Oct/17 ] |
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Found to be associated with the BEE board revision. All three older boards have been retired. |