Add polarity to FPGA clock description

The FPGA clock description does not separate logical from electronic polarity. "turn IR on" always drives the signal high, instead of always closing the switch. This has occasionally been confusing, but the requirement to support two versions of the ADC board, one with normally-open switches and one with normally-closed switches makes it nutty.

Add a polarity flag to the low-level clock class, and allow overriding for the old ADCs.