Maintain branch for FPGA image for JHU Optics Lab

The cabling in the JHU Optics Lab is a one-off oddity. This causes the ADC output timing to be mishandled.

No one really wants to spend the time to identify the cabling issue right now, and maybe never. So make (and maintain) a branch which latches the ADC output bits on the rising edge of the clock signal instead of the falling edge. A one-line change.

FPGA version 0xbeeaa083 already running. I just want to label it.