FEE LVDS chips fragile; enable FPGA tristate power control.

Change FPGA CN4/9 outputs to tristate LVDS.

The FEE LVDS chips are fragile, and our LVDS clock outputs cannot be energized when the FEE is connected/powered up or down. So we:

• changed all the CN4/9 outputs from OBUFDS to OBUFTDS
• add bit 7 to the PCI control word. If set, the CN4/9 tristate control bits are enabled.

[ Did this work on a "tri-state" branch a couple of months ago. Had it working but subsequently broke the control word logic when trying to be clever. Will rename "tri-state" branch when this ticket gets created. ]