[ics_xcu_fpga] CCD readouts show one wrapped row and col

This issue was initially filed into JIRA by 'cloomis' at 08/Jan/16 6:39 PM as ICS-20.
This issue was assigned to 'unassigned', set as '2015-10 Detector Readout' sprint.

Current images from the FPGA come with the last row and last columns in the 0th row and column. To correct this, the fpga.geom.Exposure reader rolls the image. This should be fixed at a lower level.

I do not think that either src/fpga.c or fpga/pyFPGA.pyx are the cause of the problem, so suspect something in the FPGA.

Note that the column roll is for the entire image, and not for each amp.

This is not critical, as no information is lost. The current data files are not corrected, but either they should be and/or a header keyword should be added.